1. Field of the Invention
The present invention relates to a layout design method for semiconductor integrated circuits, more particularly to a layout design method that reduces power consumption.
2. Description of the Related Art
In addition to high integration and high processing speed, lower power consumption is an important requirement for semiconductor integrated circuits. Power consumption is generally categorized into two types: dynamic or active power consumption, caused by operation; and standby power consumption, caused by current leakage.
With the continually shrinking feature sizes in recent fabrication processes, the gate lengths of the metal oxide semiconductor field-effect transistors (MOSFETs) in semiconductor integrated circuits have been reduced to the point where current leakage cannot be ignored. A known countermeasure to current leakage is to design a semiconductor integrated circuit as a combination of cells taken from two types of cell libraries. One type (referred to as a high threshold voltage or Hvt cell library below) uses MOSFETs having a relatively high threshold voltage, a relatively small leakage current, and a relatively low operating speed; the other type (referred to as a low threshold voltage or Lvt cell library below) uses MOSFETs having a relatively low threshold voltage, a relatively large leakage current and a relatively high operating speed. In a typical example, Lvt cells operate twice as fast as Hvt cells but have twenty times as much leakage current. Using TDelay to denote propagation delay and ILeak to denote leakage current, this can be expressed as follows:TDelayLvt:TDelayHvt=1:2ILeakLvt:ILeakHvt=1:0.05
In the logic synthesis stage before the layout process, Lvt cell libraries are generally used in order to satisfy constraints related to operating speed, because if Hvt cell libraries were to be used to reduce leakage current, operating speed would be inadequate. A conventional layout design method for semiconductor integrated circuits, more particularly, a method that reduces their leakage current, then proceeds as follows.
Referring to FIG. 1, this method utilizes a pre-layout net list 103 comprising data taken from Lvt cell libraries, layout data 104 comprising data obtained immediately after the layout process; and layout data 105 comprising layout data taken from both Lvt and Hvt cell libraries.
In this method, first a placement layout process 30 uses the pre-layout net list 103 to position cells. A routing layout process 40 then routes wiring paths among the cells and accordingly generates the layout data 104. Next, a delay time analysis process 50 is carried out. If, as a result, the propagation delay time of a signal does not satisfy operational constraints, a timing correction process 51 carries out resizing or other appropriate processing on the cells and the layout process returns to the placement layout process 30.
When the propagation delay times of all signals satisfy the operational constraints in the delay time analysis process 50, the design process proceeds to a non-critical path replacement process 60, in which Lvt cells on non-critical paths are replaced by Hvt cells with the same logic and size to generate the second layout data 105. Then a hold timing analysis 70 is carried out. If a hold error occurs, another timing correction process 71 inserts delay adjustment cells and the design process returns to the placement layout process 30. When all operational constraints are satisfied, the layout design ends.
The non-critical paths in the above method are paths with ample timing margins. Because Lvt cells are replaced with Hvt cells only on these paths, the proportion of Hvt cells remains comparatively low and current leakage remains comparatively high, sometimes too high to meet system power consumption specifications.